SCAIL Projects
Petabyte-scale memory systems
Systems with terabytes to petabytes of memory are on the horizon due to new memory technologies such as persistent memory. While large-memory systems create new opportunities, they also present challenges for memory management. Previously acceptable bookkeeping overheads or policies, when scaled up to large systems, often have unacceptable results. We have designed the 0sim simulator to study these issues, and are looking into principled memory management techniques that improve system behavioral consistency and performance.
Relevant Papers
- Mark Mansi and Michael M. Swift. Preparing systems software for a world with terabyte-scale memories with 0sim. To appear in Proceedings of the 25h ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2020), March 2020.
Secure isolation platforms
In the recent years, clouds providers are moving towards serverless infrastructure with the pay as you use model. To deploy these lightweight serverless functions, they use different isolation platforms ranging from docker containers to Google’s gVisor and AWS Firecracker. A common theme across these platforms are the twin goals of strong isolation and high performance. In this project, we are looking at ways to measure the isolation of these isolation platforms and guide developers to use the right isolation platform for their workloads.
Relevant Papers
- Anjali, Tyler Caraza-Harter and Michael M. Swift. Blending Containers and Virtual Machines: A Study of Firecracker and gVisor. To appear in Proceedings of the 16th International Conference on Virtual Execution Environments (VEE '20). March, 2020.
- Liang Wang, Mengyuan Li, Yinqian Zhang, Thomas Ristenpart and Michael Swift. Peeking Behind the Curtains of Serverless Platforms. In Proceedings of the 2018 USENIX Annual Technical Conference (USENIX ATC'18), July 2018
Persistent memory
Emerging non-volatile memory (NVM) technologies such as Intel's Optane Persistent memory (PM) pair the high performance and byte-addressability of DRAM with the durability of disks. These memories enable a new class of recoverable applications with in-memory data structures that survive system crashes and power failures. To be able to recover correctly from crashes, memory should be left in a consistent state before the crash. Ensuring consistency requires that updates to persistent memory are ordered. However, the cost of ordering and durability is very high in currently available systems. We explore software techniques that can reduce the ordering constraints in applications using PM, thereby improving the applications' performance (Don't Persist All, MOD). We also develop hardware architectures that alleviate the cost of ordering and improve the overall performance (ASAP).
Relevant Papers
- Sujay Yadalam, Nisarg Shah, Xiangyao Yu and Michael M. Swift. ASAP: A Speculative Approach to Persistence. To appear in Proceedings of the 28th IEEE International Symposium on High-Performance Computer Architecture (HPCA '22), February 2022.
- Swapnil Haria, Mark D. Hill and Michael M. Swift. MOD: Minimally Ordered Durable Datastructures for Persistent Memory. To appear in Proceedings of the 25h ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2020), March 2020.
- Pratyush Mahapatra, Mark D. Hill, Michael M. Swift. Don't Persist All : Efficient Persistent Data Structures arXiv:1905.13011, May 2019.
- Nikhita Kunati and Michael M. Swift. Implementation of Direct Segments on a RISC-V Processor. In Second Workshop on Computer Architecture Research with RISC-V (CARRV), June 2018.
- Swapnil Haria, Mark D. Hill, Michael M. Swift. Devirtualizing Memory for Heterogeneous Systems. In Proceedings of the 23nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2018), March 2018.
Intelligent memory systems
Intelligent memory systems (IMS) are a new and upcoming type of accelerator based system that aim to bring computation close to the data being operated on in memory. Near-memory accelerators promise improved performance for memory-intensive workloads such as data management. But, the software and hardware overhead of offloading tasks to accelerators can greatly reduce the effective performance gain. For example, IOMMU overheads for address translation and protection can greatly reduce effective memory bandwidth. Our work seeks to design an efficient, low latency application-level interface to near-memory accelerators with a co-designed memory virtualization architecture for high performance. We leverage past work on de-virtualized memory, and recent hardware designs on efficient hardware queues.
Additionally, IMS performance can be adversely affected by workloads that exhibit poor cache utilization, low channel level parallelism, and unnecessary/excessive data movement. Traditional CPU's provide a rich assortment of hardware performance counters and software programming tools to identify these patterns. However, in an accelerator environment, resources are constrained, the performance impact of misusing hardware is high, and such performance counters may be unavailable. We are currently investigating methods to provide lightweight software-based data collection tools that utilize the IMS on-board processor. With these tools, we aim to help developers for IMS applications identify problematic access patterns so they may make the necessary changes to improve application performance.